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11	RISC versus CISC: A Tale of Two Chips Dileep Bhandarkar Intel Corporation Santa Clara, California, USA Abstract Add to Reading List Source URL: www.cs.inf.ethz.ch Language: English - Date: 1999-10-20 11:54:48 Central processing unit Instruction set architectures CPU cache Cache Computer memory Pentium Pro P5 DEC Alpha Alpha 21164 Computer architecture Computer hardware Computing
12	Previous chapter 19 pentium: not the same old song Add to Reading List Source URL: downloads.gamedev.net Language: English - Date: 2011-08-09 01:03:16 Instruction set architectures Pentium Pro CPU cache X86 CPUID Pentium Branch predictor Superscalar Intel Core Computer architecture Computing Computer hardware
13	To appear in Proceedings of the 25th International Symposium on Computer Architecture, Barcelona, Spain, June[removed]Performance Characterization of a Quad Pentium Pro SMP Using OLTP Workloads Kimberly Keeton, David A. Add to Reading List Source URL: www.hpl.hp.com Language: English* - Date: 2002-03-06 19:31:06 Computer memory CPU cache Cache Pentium Pro Microarchitecture Pentium Montecito Pentium II Computer hardware Central processing unit Computer architecture
14	Performance Characterization of a Quad Pentium Pro SMP Using OLTP Workloads1 Kimberly Keeton, David A. Patterson, Yong Qiang He+, Roger C. Raphael+, and Walter E. Baker# Computer Science Division Add to Reading List Source URL: www.hpl.hp.com Language: English* - Date: 2002-03-06 19:31:08 Computer engineering Computer memory CPU cache Cache Microprocessors Pentium Pro Microarchitecture Pentium Pentium II Computer hardware Computer architecture Central processing unit
15	Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Datasheet Product Features ■ Add to Reading List Source URL: download.intel.com Language: English - Date: 2014-11-25 18:02:28 Pentium II Slot 1 Celeron Multi-core processor Pentium Pro Intel Core Pentium Front-side bus Pentium OverDrive Computer hardware CPU sockets Pentium III
16	Operating System Benchmarking in the Wake of Lmbench: A Case Study of the Performance of NetBSD on the Intel x86 Architecture Aaron B. Brown Margo I. Seltzer Harvard University {abrown,margo}@eecs.harvard.edu Add to Reading List Source URL: www.eecs.harvard.edu Language: English - Date: 2009-09-06 12:29:23 CPU cache Pentium Pro P5 Memory bandwidth Cache Benchmark Dynamic random-access memory Alpha 21164 Loop nest optimization Computer memory Computer hardware Computing
17	I NFORMATION LINK January 1997 Add to Reading List Source URL: www.nd.gov Language: English - Date: 2010-12-30 15:04:52 Pentium Pro Cyrix 6x86 X86 Cyrix P5 Windows NT Pentium compatible processor Silicon Integrated Systems Cyrix Cx5x86 Computer architecture Computing Microsoft Windows
18	PDF Document Add to Reading List Source URL: www.npa.org Language: English - Date: 1999-02-01 03:00:00 CPU cache Cache Central processing unit Slot 1 Pentium Pro Pentium II Pentium Clock rate Intel Core Computer hardware Computer architecture Computer memory
19	Python Standard Library: Data Representation 4-1 Data Representation "PALO ALTO, Calif. — Intel says its Pentium Pro and new Pentium II Add to Reading List Source URL: effbot.org Language: English - Date: 2014-05-31 19:27:50 Persistence Data types Data transmission Procedural programming languages Scripting languages Serialization Python D Endianness Computing Software engineering Computer programming
20	I NFORMATION LINK January 1997 Add to Reading List Source URL: www.nd.gov Language: English - Date: 2010-12-30 15:04:52 Pentium Pro Cyrix 6x86 X86 Cyrix P5 Windows NT Pentium compatible processor Silicon Integrated Systems Cyrix Cx5x86 Computer architecture Computing Microsoft Windows